While more convenient life for human being is ongoing and driven by rapid changing technology, demands for electronic products tend to deliver multiple functionality, high-speed transmission of electronic signals, and high density of circuit components. Particularly for consuming electronic products, the larger number of passive components embedded in the IC is, the more functions performed thereby will be. Therefore, how to accommodate the large number of electronic components in the limited packaging space has become a technical bottleneck to be overcome. To solve the above-mentioned problem, package technique is guided by market segments to progressively develop towards the level of Sip (system in package), and the embedded technology and the build-up technology become crucial. Components buried interiorly shorten the packaging space extensively, where more components with high performance can be integrated into the saving space within the package. Furthermore, the build-up technology increases high density of the circuit and reduces the thickness of components, thereby raising the overall packaging density of the product.
However, the size of layout and the space between electronic components on the chip become much tinier due to the extensively space-limited packaging and higher contact density. Therefore, stresses are easily provoked to gather in terminal contacts of the chip or via holes for rerouting when the environment is changed by different factors and exterior forces. Those areas on the chip with higher stress usually cause the terminal contacts to be damaged or cause the conducting wires to be broken, thereby disabling the chip.
Please referring to FIG. 1, the U.S. Pat. No. 5,757,072 disclosed that the protective cap 16 is used to cover the chip 12a and the positive and passive components 12 which are sensible and easily interfered by exterior forces, in order to protect the overall manufacturing process from contamination within the high-density interconnecting structure 10. However, in this patent, the protective cap 16 needs to be additionally manufactured and the structure thereof is quite complicated, and thus the cost therefor is high.
Please referring to FIG. 2, the U.S. Pat. No. 6,586,836 disclosed that the second die assembly 162 is used to reduce warpage of the microelectronic die, which prevents the microelectronic die from being disabled due to the gathering stress resulting from warpage. However, this is only applied in the microelectronic dice with multiple chips. As described above, the technique is applied in limited fields and its procedures are more complicated.
Please referring to FIG. 3, the U.S. Pat. No. 5,866,952 disclosed that the compliant material 17 is deposited around the chips 14 and 20, and then a mold form is positioned around the chips prior to molding a polymeric substrate therearound within the high-density interconnecting structure 26. Hence, the chip is normally operated by preventing from the gathering stress thereon.
In order to overcome the drawbacks in the prior art, a structure for protecting an electronic package contact and the method thereof are provided. The particular designs in the present invention not only solve the problems described above, but also are easy to be implemented. Thus, the invention has the utility for the industry.